Muqsetin Kabir’s Post

________________TAHOE_______________ ___________IC MASK DESIGN__________ Analog Layout: Project SI_SN Technology Node: GPDK - 45nm Highest Routing - Metal 3 Hook Power Rail - Metal 4 Guard Ring - N Ring Using Dummy device Different Body connection Physical Verification using assura tools: LVS, DRC PR boundary at (0,0)

Excited to share a recent milestone achieved during the CND training: completing a project that focused on design verification and post-layout simulation for a Barrel Shifter! 🔍 Project Overview: Design Verification: Ensured design robustness through meticulous checks including DRC, LVS, and PEX, ensuring our Barrel Shifter met stringent specifications. Post-Layout Simulation: Delved into the post-layout simulation to assess performance and stability, specifically targeting the Arithmetic Shift function with parasitic effects factored in. 💡 Key Learnings: Gained a deeper understanding of design verification methodologies, emphasizing reliability in complex IC designs like the Barrel Shifter. Acquired hands-on experience in post-layout simulation, refining skills in performance optimization and stability assessment. 🌟 Achievements: Successfully completed DRC, LVS, and PEX checks, ensuring compliance with industry standards and project requirements. Conducted comprehensive post-layout simulations, validating the Barrel Shifter's functionality and confirming its Arithmetic Shift capability amidst parasitic influences. #DesignVerification #PostLayoutSimulation #BarrelShifter #SemiconductorDesign #CNDCertification

The emitter follower circuit provides a high impedance input & unity voltage gain making it an ideal buffer stage to prevent loading on a critical circuit. The transistor emitter follower is one of the basic transistor circuit formats and as such it is a very useful tool for any circuit designer. Discover more now: https://lnkd.in/et2vtFqd #emitterfollower #transistor #circuitdesign

Designing 4543 CMOS Clock Altium Pt82

5 reasons to run a DRC for your #PCBDesign DRC detects electrical and physical violations such as power ground shorts, misaligned vias, and missing pins. It offers several advantages, including reduction in prototype iteration, efficient use of board space, and ensuring compliance with design requirements. -- Read the article for more: https://lnkd.in/gD39a_cY -- Send this to #PCBdesigners and hardware engineers. #pcblayout #circuitboarddesign #electricalengineering

5 reasons to run a DRC for your #PCBDesign DRC detects electrical and physical violations such as power ground shorts, misaligned vias, and missing pins. It offers several advantages, including reduction in prototype iteration, efficient use of board space, and ensuring compliance with design requirements. -- Read the article for more: https://lnkd.in/grDZ_f4P -- Send this to #PCBdesigners and hardware engineers. #pcblayout #circuitboarddesign #electricalengineering

Designing 4543 CMOS Clock Altium Pt167

Designing 4543 CMOS Clock Altium Pt137